Synapse: Virtualizing Match Tables in Programmable Hardware

TL;DR

Synapse introduces a virtualized match table framework for programmable hardware, enabling dynamic, efficient, and scalable network packet processing by combining on-chip and off-chip memory with adaptive resource allocation.

Contribution

It presents a novel VMT framework inspired by OS virtual memory, with a hybrid memory system and dynamic allocation optimization for high-performance network processing.

Findings

Prototype on FPGA demonstrates scalability and effectiveness.

Hybrid memory system balances speed and scalability.

Dynamic allocation improves resource utilization.

Abstract

Efficient network packet processing increasingly demands dynamic, adaptive, and run-time resizable match table allocation to handle the diverse and heterogeneous nature of traffic patterns and rule sets. Achieving this flexibility at high performance in hardware is challenging, as fixed resource constraints and architectural limitations have traditionally restricted such adaptability. In this paper, we introduce Synapse, an extension to programmable data plane architectures that incorporates the Virtual Matching Table (VMT) framework, drawing inspiration from virtual memory systems in Operating Systems (OSs), but specifically tailored to network processing. This abstraction layer allows logical tables to be elastic, enabling dynamic and efficient match table allocation at runtime. Our design features a hybrid memory system, leveraging on-chip associative memories for fast matching of the most popular rules and off-chip addressable memory for scalable and cost-effective storage. Furthermore, by employing a sharding mechanism across physical match tables, Synapse ensures that the power required per key match remains bounded and proportional to the key distribution and the size of the involved shard. To address the challenge of dynamic allocation, we formulate and solve an optimization problem that dynamically allocates physical match tables to logical tables based on pipeline usage and traffic characteristics at the millisecond scale. We prototype our design on FPGA and develop a simulator to evaluate the performance, demonstrating its effectiveness and scalability.