Lightweight LIF-only SNN accelerator using differential time encoding

TL;DR

This paper presents a lightweight, efficient hardware accelerator for LIF-only SNNs with a novel differential time encoding method, achieving high accuracy and fast inference on FPGA and ASIC platforms.

Contribution

It introduces a specialized hardware architecture for LIF-only SNNs and a new differential time encoding technique for efficient spike data processing.

Findings

Achieves >99% accuracy on MNIST

Inference times of 0.29ms on FPGA and 0.17ms on ASIC

Demonstrates efficient merging of spikes in hardware

Abstract

Spiking Neural Networks (SNNs) offer a promising solution to the problem of increasing computational and energy requirements for modern Machine Learning (ML) applications. Due to their unique data representation choice of using spikes and spike trains, they mostly rely on additions and thresholding operations to achieve results approaching state-of-the-art (SOTA) Artificial Neural Networks (ANNs). This advantage is hindered by the fact that their temporal characteristic does not map well to already existing accelerator hardware like GPUs. Therefore, this work will introduce a hardware accelerator architecture capable of computing feedforward LIF-only SNNs, as well as an accompanying encoding method to efficiently encode already existing data into spike trains. Together, this leads to a design capable of >99% accuracy on the MNIST dataset, with ~0.29ms inference times on a Xilinx Ultrascale+ FPGA, as well as ~0.17ms on a custom ASIC using the open-source predictive 7nm ASAP7 PDK. Furthermore, this work will showcase the advantages of the previously presented differential time encoding for spikes, as well as provide proof that merging spikes from different synapses given in differential time encoding can be done efficiently in hardware.