An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation

TL;DR

This paper presents an integrated UVM-TLM co-simulation framework for RISC-V processors that combines functional verification and performance evaluation, achieving faster simulation speeds and improved verification coverage.

Contribution

It introduces a configurable UVM-TLM model for RISC-V cores that enables unified verification and early performance assessment within a single environment.

Findings

Functional correctness validated against Spike simulator.

Achieved significant speedup over RTL simulation.

Facilitated architectural exploration with acceptable fidelity.

Abstract

The burgeoning RISC-V ecosystem necessitates efficient verification methodologies for complex processors. Traditional approaches often struggle to concurrently evaluate functional correctness and performance, or balance simulation speed with modeling accuracy. This paper introduces an integrated co-simulation framework leveraging Universal Verification Methodology (UVM) and Transaction-Level Modeling (TLM) for RISC-V processor validation. We present a configurable UVM-TLM model (vmodel) of a superscalar, out-of-order RISC-V core, featuring key microarchitectural modeling techniques such as credit-based pipeline flow control. This environment facilitates unified functional verification via co-simulation against the Spike ISA simulator and enables early-stage performance assessment using benchmarks like CoreMark, orchestrated within UVM. The methodology prioritizes integration, simulation efficiency, and acceptable fidelity for architectural exploration over cycle-level precision. Experimental results validate functional correctness and significant simulation speedup over RTL approaches, accelerating design iterations and enhancing verification coverage.