Automated SAR ADC Sizing Using Analytical Equations

TL;DR

This paper introduces an automated methodology for designing SAR ADCs that uses analytical equations and a dual optimization scheme to efficiently determine transistor sizes from specifications, reducing manual effort.

Contribution

It presents a novel dual optimization framework and dependency graph-based system for fully automated SAR ADC sizing from specifications to transistor parameters.

Findings

Achieved high SNDR in case studies.

Reduced design time compared to manual methods.

Successfully met all design constraints.

Abstract

Conventional analog and mixed-signal (AMS) circuit designs heavily rely on manual effort, which is time-consuming and labor-intensive. This paper presents a fully automated design methodology for Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) from performance specifications to complete transistor sizing. To tackle the high-dimensional sizing problem, we propose a dual optimization scheme. The system-level optimization iteratively partitions the overall requirements and analytically maps them to subcircuit design specifications, while local optimization loops determines the subcircuits' design parameters. The dependency graph-based framework serializes the simulations for verification, knowledge-based calculations, and transistor sizing optimization in topological order, which eliminates the need for human intervention. We demonstrate the effectiveness of the proposed methodology through two case studies with varying performance specifications, achieving high SNDR and low power consumption while meeting all the specified design constraints.