MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units

TL;DR

This paper presents a minimal gated recurrent unit architecture optimized for embedded systems, utilizing switched-capacitor circuits for in-memory computation, and demonstrates its effectiveness through hardware-compatible simulations.

Contribution

A novel minimal GRU design with hardware-compatible mixed-signal implementation using switched-capacitor circuits for efficient in-memory RNN computation.

Findings

Hardware-compatible mixed-signal implementation verified in simulations

Achieved in-memory computation with commodity circuits

Benchmark results demonstrate effective time series processing

Abstract

Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes. We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model.