CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

TL;DR

This paper demonstrates industry-grade, wafer-scale superconducting qubits with median energy relaxation times up to 100 microseconds and individual devices reaching 200 microseconds, surpassing previous performance benchmarks.

Contribution

It introduces a CMOS-compatible, wafer-scale fabrication process for superconducting qubits with high yield and exceptional energy relaxation times, advancing scalable quantum computing technology.

Findings

99.7% fabrication yield across 10,000 junctions

Median T1 of up to 100 microseconds

Individual qubits approaching 200 microseconds in relaxation time

Abstract

We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.