GDNTT: an Area-Efficient Parallel NTT Accelerator Using Glitch-Driven Near-Memory Computing and Reconfigurable 10T SRAM

TL;DR

This paper introduces GDNTT, a highly parallel, area-efficient NTT accelerator that leverages glitch-driven near-memory computing and reconfigurable SRAM to significantly improve throughput and energy efficiency for post-quantum cryptography.

Contribution

It presents a novel NTT accelerator design combining glitch-driven near-memory computing with reconfigurable 10T SRAM for enhanced performance and area efficiency.

Findings

Achieves up to 28x throughput-per-area improvement.

Reduces latency of butterfly operations with glitch generator.

Supports real-time, low-power cryptographic applications.

Abstract

With the rapid advancement of quantum computing technology, post-quantum cryptography (PQC) has emerged as a pivotal direction for next-generation encryption standards. Among these, lattice-based cryptographic schemes rely heavily on the fast Number Theoretic Transform (NTT) over polynomial rings, whose performance directly determines encryption/decryption throughput and energy efficiency. However, existing software-based NTT implementations struggle to meet the real-time performance and low-power requirements of IoT and edge devices. To address this challenge, this paper proposes an area-efficient highly parallel NTT accelerator with glitch-driven near-memory computing (GDNTT). The design integrates a 10T SRAM for data storage, enabling flexible row/column data access and streamlining circuit mapping strategies. Furthermore, a glitch generator is incorporated into the near-memory computing unit, significantly reducing the latency of butterfly operations. Evaluation results show that the proposed NTT accelerator achieves a 1.5~28* improvement in throughput-per-area compared to the state-of-the-art.