A two-stage time-stretching TDC with discrete components

TL;DR

This paper introduces a low-cost, modular two-stage time-stretching TDC using discrete components, achieving sub-100 ps resolution and rapid conversion times, suitable for particle physics applications and future ASIC development.

Contribution

It presents a novel two-stage time-stretching architecture with onboard calibration, demonstrating high resolution and fast conversion in a low-power FPGA-based system for particle physics.

Findings

Achieved under 100 ps time resolution.

Conversion time below 300 ns for 10 ns input range.

Demonstrated suitability for particle physics timing applications.

Abstract

This paper presents the design and testing of a time-stretching-based time-to-digital converter (TDC) implemented with discrete components. The TDC utilizes capacitor charging and discharging to achieve a time resolution of under 100 ps using a 100 MHz clock counter on a low-power, low-cost FPGA, achieving a time amplification factor of over 100. A two-stage time-stretching architecture is employed to reduce the conversion time to below 300 ns for a 10 ns input range. An onboard calibration system, including a pulse generation circuit, is implemented, and calibration results are presented. This system serves as a proof-of-concept platform for circuit optimization toward an ASIC implementation of a front-end TDC targeting future 4D pixel detectors at hadron colliders, with goals of sub-50 ps resolution and power consumption at the $\mu$W/channel level. Additionally, the design offers a modular, low-cost solution for extracting signal arrival times with 100 ps precision in particle physics experiments, such as photoelectron timing extraction for photodetector readout in neutrino experiments.