Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators

TL;DR

This paper evaluates the scalability of binary and ternary CNN workloads on RRAM-based compute-in-memory accelerators, focusing on accuracy, energy efficiency, and the impact of circuit parasitics and ADC resolution.

Contribution

It introduces novel simulation models for parasitics and ADC effects, and provides a comparative analysis of binary and ternary CNNs on RRAM CIM architectures.

Findings

Ternary CNNs are more resilient to wire parasitics and low ADC resolution.

Ternary CNNs reduce energy efficiency by approximately 40%.

The proposed models achieve high accuracy with errors below 0.15%.

Abstract

The increasing computational demand of Convolutional Neural Networks (CNNs) necessitates energy-efficient acceleration strategies. Compute-in-Memory (CIM) architectures based on Resistive Random Access Memory (RRAM) offer a promising solution by reducing data movement and enabling low-power in-situ computations. However, their efficiency is limited by the high cost of peripheral circuits, particularly Analog-to-Digital Converters (ADCs). Large crossbars and low ADC resolutions are often used to mitigate this, potentially compromising accuracy. This work introduces novel simulation methods to model the impact of resistive wire parasitics and limited ADC resolution on RRAM crossbars. Our parasitics model employs a vectorised algorithm to compute crossbar output currents with errors below 0.15% compared to SPICE. Additionally, we propose a variable step-size ADC and a calibration methodology that significantly reduces ADC resolution requirements. These accuracy models are integrated with a statistics-based energy model. Using our framework, we conduct a comparative analysis of binary and ternary CNNs. Experimental results demonstrate that the ternary CNNs exhibit greater resilience to wire parasitics and lower ADC resolution but suffer a 40% reduction in energy efficiency. These findings provide valuable insights for optimising RRAM-based CIM accelerators for energy-efficient deep learning.