Efficient Implementation of RISC-V Vector Permutation Instructions

TL;DR

This paper presents a unified microarchitecture for efficiently executing all RISC-V vector permutation instructions, reducing hardware costs and maintaining fixed latency, validated through implementation in a 7 nm open-source processor.

Contribution

A novel unified microarchitecture design that efficiently executes all RVV permutation instructions with minimal area overhead in a RISC-V vector processor.

Findings

Only 1.5% area overhead in the vector processor.

Area overhead decreases as minimum element width increases.

Supports single-cycle execution for vectors up to 256 bits.

Abstract

RISC-V CPUs leverage the RVV (RISC-V Vector) extension to accelerate data-parallel workloads. In addition to arithmetic operations, RVV includes powerful permutation instructions that enable flexible element rearrangement within vector registers --critical for optimizing performance in tasks such as matrix operations and cryptographic computations. However, the diverse control mechanisms of these instructions complicate their execution within a unified datapath while maintaining the fixed-latency requirement of cryptographic accelerators. To address this, we propose a unified microarchitecture capable of executing all RVV permutation instructions efficiently, regardless of their control information structure. This approach minimizes area and hardware costs while ensuring single-cycle execution for short vector machines (up to 256 bits) and enabling efficient pipelining for longer vectors. The proposed design is integrated into an open-source RISC-V vector processor and implemented at 7 nm using the OpenRoad physical synthesis flow. Experimental results validate the efficiency of our unified vector permutation unit, demonstrating that it only incurs 1.5% area overhead to the total vector processor. Furthermore, this area overhead decreases to near-0% as the minimum supported element width for vector permutations increases.