Regular mixed-radix DFT matrix factorization for in-place FFT accelerators

TL;DR

This paper introduces a regular mixed-radix DFT matrix factorization method tailored for in-place FFT accelerators, enhancing understanding of architecture needs and simplifying algorithm development and correctness verification.

Contribution

It proposes a novel mixed-radix factorization aligned with vector memory based FFT architectures, aiding in design and correctness proof.

Findings

Improved understanding of architecture requirements

Simplified development of conflict-free addressing schemes

Facilitated correctness proofs for FFT algorithms

Abstract

The generic vector memory based accelerator is considered which supports DIT and DIF FFT with fixed datapath. The regular mixed-radix factorization of the DFT matrix coherent with the accelerator architecture is proposed and the correction proof is presented. It allows better understanding of architecture requirements and simplifies the developing and proving correctness of more complicated algorithms and conflict-free addressing schemes.