Extend IVerilog to Support Batch RTL Fault Simulation

TL;DR

This paper enhances IVerilog to enable batch RTL fault simulation by integrating event-driven and concurrent algorithms, significantly improving simulation performance for functional safety verification.

Contribution

The paper introduces an extended IVerilog simulator supporting batch RTL fault simulation with combined algorithms, offering substantial performance gains.

Findings

Achieves 2.2× speedup over commercial simulator

Achieves 3.4× speedup over open-source simulator

Improves efficiency in RTL fault simulation for safety standards

Abstract

The advancement of functional safety has made RTL-level fault simulation increasingly important to achieve iterative efficiency in the early stages of design and to ensure compliance with functional safety standards. In this paper, we extend IVerilog to support batch RTL fault simulation and integrate the event-driven algorithm and the concurrent fault simulation algorithm. Comparative experiments with a state-of-the-art commercial simulator and an open-source RTL fault simulator demonstrate that our simulator achieves a performance improvement of 2.2$\times$ and 3.4$\times$, respectively.