Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process

TL;DR

This paper presents a detailed characterization of a 65 nm CMOS digital pixel test structure for future high-energy physics detectors, demonstrating its efficiency, radiation hardness, and low-power operation.

Contribution

It provides new insights into the performance and robustness of 65 nm CMOS MAPS technology under various radiation and operational conditions.

Findings

High detection efficiency confirmed after irradiation

Low fake-hit rate achieved in tests

Sensor maintains performance at low power levels

Abstract

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07% X/X$_{0}$ per layer and have a low power consumption in the active area of 40 mW/cm$^{2}$ by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 mW/cm$^{2}$, while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7-28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0-45$^\circ$.