Planar fault-tolerant circuits for non-Clifford gates on the 2D color code

TL;DR

This paper presents a scalable, planar fault-tolerant circuit design for implementing non-Clifford gates on a 2D color code, enabling efficient quantum computation with minimal hardware complexity.

Contribution

It introduces a novel circuit construction based on a spacetime path integral and tensor network approach, achieving fault tolerance with simple gates and measurements on a 2D chip.

Findings

Circuit implementation of logical T gates and magic state preparation

Fault tolerance achieved using extended color-code matching decoders

Compatible with 2D nearest-neighbor qubit architectures

Abstract

We introduce a family of scalable planar fault-tolerant circuits that implement logical non-Clifford operations on a 2D color code, such as a logical $T$ gate or a logical non-Pauli measurement that prepares a magic $|T\rangle$ state. The circuits are relatively simple, consisting only of physical $T$ gates, $CX$ gates, and few-qubit measurements. They can be implemented with an array of qubits on a 2D chip with nearest-neighbor couplings, and no wire crossings. The construction is based on a spacetime path integral representation of a non-Abelian 2+1D topological phase, which is related to the 3D color code. We turn the path integral into a circuit by expressing it as a spacetime $ZX$ tensor network, and then traversing it in some chosen time direction. We describe in detail how fault tolerance is achieved using a "just-in-time" decoding strategy, for which we repurpose and extend state-of-the-art color-code matching decoders.