3D-Integrated Superconducting qubits: CMOS-Compatible, Wafer-Scale Processing for Flip-Chip Architectures

TL;DR

This paper introduces a CMOS-compatible, wafer-scale 3D integration process for superconducting qubits using flip-chip bonding, enabling scalable quantum computing architectures with high coherence times.

Contribution

It develops a novel 3D integration method for superconducting qubits compatible with CMOS standards, including new microbump technology and fabrication techniques.

Findings

Superconducting transition observed in metal stacks.

RF signal transfer through microbump with negligible attenuation.

Qubits exhibit energy relaxation times up to 15 microseconds.

Abstract

In this article, we present a technology development of a superconducting qubit device 3D-integrated by flip-chip-bonding and processed following CMOS fabrication standards and contamination rules on 200 mm wafers. We present the utilized proof-of-concept chip designs for qubit- and carrier chip, as well as the respective front-end and back-end fabrication techniques. In characterization of the newly developed microbump technology based on metallized KOH-etched Si-islands, we observe a superconducting transition of the used metal stacks and radio frequency (RF) signal transfer through the bump connection with negligible attenuation. In time-domain spectroscopy of the qubits we find high yield qubit excitation with energy relaxation times of up to 15 us.