Scalable 49-Channel Neural Recorder with an Event-Driven Ramp ADC and PCA Compression in 28 nm CMOS

TL;DR

This paper presents a scalable 49-channel neural recorder in 28nm CMOS that uses an event-driven ramp ADC and PCA-based compression to reduce data size while maintaining high spike sorting accuracy, enabling efficient wireless neural data transmission.

Contribution

It introduces a novel integrated circuit with event-driven ADC and PCA compression, achieving significant data reduction and efficient neural recording in a compact, low-power design.

Findings

8.8-fold data compression compared to raw spikes

328-fold data reduction relative to raw signals

74.9% spike sorting accuracy maintained

Abstract

Neural interfaces advance neuroscience research and therapeutic innovations by accurately measuring neuronal activity. However, recording raw data from numerous neurons results in substantial amount of data and poses challenges for wireless transmission. While conventional neural recorders consume energy to digitize and process the full neural signal, only a fraction of this data carries essential spiking information. Leveraging on this signal sparsity, this paper introduces a neural recording integrated circuit in TSMC 28nm CMOS. It features an event-driven ramp analog-to-digital converter, and a spike compression module based on principal component analysis. The circuit consists of 49 channels, each occupying an on-chip area of 50 $\times$ 60 $\mu$m$^2$. The circuit measures 1370 $\times$ 1370 $\mu$m$^2$ and consumes 534 $\mu$W. Compression testing on a synthetic dataset demonstrated an 8.8-fold reduction compared to raw spikes and a 328-fold reduction relative to the raw signal. This compression approach maintained a spike sorting accuracy of 74.9%, compared to the 79.5% accuracy obtained with the raw signal. The paper details the architecture and performance outcomes of the neural recording circuit and its compression module.