CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

TL;DR

CVA6S+ is an enhanced open-source superscalar RISC-V core that significantly improves performance and cache bandwidth, making it suitable for high-end embedded applications like automotive systems.

Contribution

The paper introduces CVA6S+, a novel superscalar RISC-V core with advanced features that boost performance and cache bandwidth with minimal area overhead.

Findings

43.5% performance improvement over scalar CVA6

10.9% performance gain over CVA6S

74.1% bandwidth increase with new cache subsystem

Abstract

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.