FPGA-based Toeplitz Strong Extractor for Quantum Random Number Generators

TL;DR

This paper presents a high-speed FPGA implementation of a Toeplitz Strong Extractor for quantum random number generators, achieving 26.57 Gbps and validated by standard randomness tests.

Contribution

It introduces a novel FPGA-based implementation of the Toeplitz Strong Extractor tailored for QRNGs, enabling high-speed post-processing.

Findings

Achieved 26.57 Gbps extraction speed.

Validated output with NIST STS 2.1.2.

Demonstrated effective randomness extraction from QRNG data.

Abstract

Quantum Random Number Generators (QRNGs) serve as high-entropy sources for Quantum Key Distribution (QKD) systems. However, the raw data from these quantum sources require post-processing to achieve a nearly uniform distribution. This work presents a state-of-the-art implementation of the Toeplitz Strong Extractor on an FPGA, achieving a benchmark extraction speed of 26.57 Gbps. A detailed implementation flow of the post-processing on the FPGA is provided, along with the execution speeds obtained for different randomness extraction ratios. Raw data from an in-house phase noise-based QRNG is processed on the FPGA using this implementation, and the output is validated using the NIST STS 2.1.2 statistical randomness test suite.