Analysis of a 3D Integrated Superconducting Quantum Chip Structure

TL;DR

This paper combines analytical and simulation methods to evaluate a 3D superconducting quantum chip architecture, analyzing how integration parameters affect quantum performance and coherence.

Contribution

It introduces a comprehensive modeling approach for 3D-integrated superconducting qubits, assessing the impact of dielectric interlayer properties on quantum metrics.

Findings

Qubit metrics are stable with substrate separation for detuned qubits.

Dielectric loss reduces qubit quality factor and relaxation time.

Stacked chip distance can be as small as 0.5 mm.

Abstract

This work presents a combined analytical and simulation-based study of a 3D-integrated quantum chip architecture. We model a flip-chip-inspired structure by stacking two superconducting qubits fabricated on separate high-resistivity silicon substrates through a dielectric interlayer. Utilizing \emph{rigorous} Ansys High-Frequency Structure Simulator (HFSS) simulations and analytical models from microwave engineering and quantum theory, we evaluate key quantum metrics such as eigenfrequencies, Q-factors, decoherence times, anharmonicity, cross-Kerr, participation ratios, and qubit coupling energy to describe the performance of the quantum device as a function of integration parameters. The integration parameters include the thickness and the quality of the dielectric interlayer. For detuned qubits, these metrics remain mostly invariant with respect to the substrate separation. However, introducing dielectric interlayer loss decreases the qubit quality factor, which consequentially degrades the relaxation time of the qubit. It is found that for the structure studied in this work, the stacked chip distance can be as small as $0.5 \text{mm}$. These findings support the viability of 3D quantum integration as a scalable alternative to planar architectures, while identifying key limitations in qubit coherence preservation due to lossy interlayer materials.