$R^4$: A Racetrack Register File with Runtime Software Reconfiguration
Christian Hakert, Shuo-Han Chen, Kay Heider, Roland K\"uhn, Yun-Chih, Chen, Jens Teubner, Jian-Jia Chen

TL;DR
This paper introduces a dynamic racetrack register file architecture that reconfigures at runtime to optimize energy efficiency and reduce shifts, leveraging static analysis and simulation for effective reconfiguration.
Contribution
It presents a novel racetrack register file design with runtime reconfiguration between horizontal and vertical modes, improving energy efficiency and performance.
Findings
Dynamic reconfiguration reduces energy consumption by up to 6 times.
Static analysis guides effective runtime allocation decisions.
The approach is validated using custom gem5 simulations.
Abstract
Arising disruptive memory technologies continuously make their way into the memory hierarchy at various levels. Racetrack memory is one promising candidate for future memory due to the overall low energy consumption, access latency and high endurance. However, the access dependent shift property of racetrack memory can make it easily a poor candidate, when the number of shifts is not properly reduced. Therefore, we explore how a register file can be constructed by using non-volatile racetrack memories with a properly reduced number of shifts. Our proposed architecture allows allocating registers in a horizontal or vertical allocation mode, where registers are either scattered across nanotracks or allocated along tracks. In this paper, we propose a dynamic approach, where the allocation can be altered at any access between horizontal and vertical. Control flow graph based static program…
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