Wildcat: Educational RISC-V Microprocessors

TL;DR

This paper explores simpler, more educationally effective RISC-V microprocessor pipeline organizations, demonstrating that shorter pipelines can outperform longer ones in clock frequency and are better suited for teaching and embedded implementation.

Contribution

It introduces and evaluates alternative pipeline organizations for RISC processors, challenging the assumption that longer pipelines always yield higher performance.

Findings

Longer pipelines do not always increase clock frequency.

A 3-stage pipeline can outperform 4- or 5-stage designs in FPGA and ASIC.

Shorter pipelines are more suitable for educational purposes.

Abstract

In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in the 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This paper examines more straightforward pipeline organizations for RISC processors that are suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process. Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.