High-Fidelity Integrated Quantum Photonic Logic Via Robust Directional Couplers

TL;DR

This paper demonstrates a passive, geometry-based design strategy for directional couplers in integrated photonic quantum circuits, significantly improving gate fidelity and robustness without active tuning.

Contribution

It introduces a stationary geometrical configuration for directional couplers that intrinsically suppresses fabrication errors, enhancing quantum gate fidelity in silicon photonic chips.

Findings

Achieved a mean gate fidelity of 93.30%, close to the theoretical limit.

Compared robust and non-robust designs, showing clear fidelity improvements.

Monte Carlo simulations confirmed the error suppression and robustness benefits.

Abstract

Scalable quantum information processing with integrated photonics requires quantum logic operations with high fidelity and robustness. Directional couplers, the fundamental elements enabling quantum interference and logic operations, are inherently sensitive to fabrication imperfections and environmental fluctuations, leading to reduced gate fidelities. Here, we experimentally demonstrate a passive design strategy that mitigates these errors by exploiting a stationary geometrical configuration in uniform directional couplers, where first-order variations in the coupling coefficient are intrinsically suppressed. The robust geometry is implemented in a silicon-on-insulator photonic chip hosting two-photon controlled-NOT (CNOT) quantum gates and its performance is directly compared to a non-optimized design. Measurements indicate a mean gate fidelity of $93.30 \pm 0.11\%$, representing a clear improvement over the non-robust implementation mean fidelity of $91.93 \pm 0.17\%$, without any active tuning or footprint increase. This performance approaches the theoretical limit of $93.78\%$, imposed by the imperfect source. Monte Carlo simulations incorporating realistic fabrication noise confirm the observed enhancement and reveal consistent suppression of gate-level error rates. These results demonstrate a compact, fabrication-tolerant building block for scalable, fault-tolerant photonic quantum circuits and highlight the power of passive geometric error mitigation in quantum hardware design.