FPGA-based Emulation and Device-Side Management for CXL-based Memory Tiering Systems
Yiqi Chen, Xiping Dong, Zhe Zhou, Zhao Wang, Jie Zhang, Guangyu Sun

TL;DR
This paper introduces HeteroBox, a FPGA-based emulation platform for CXL memory systems, and HeteroMem, a device-side memory tiering system that improves performance and transparency in heterogeneous memory architectures.
Contribution
The paper presents a configurable FPGA emulation platform for CXL memory systems and a novel hardware-managed tiering system that enhances performance and transparency.
Findings
HeteroBox accurately emulates CXL memory architectures.
HeteroMem improves application performance by up to 16.2%.
HeteroMem operates transparently to the CPU.
Abstract
The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory systems where CPU access to various endpoints differs in latency and bandwidth. Effective tiered memory management is essential for optimizing system performance in such systems. However, designing an effective memory tiering system for CXL-extended heterogeneous memory faces challenges: 1) Existing evaluation methods, such as NUMA-based emulation and full-system simulations like GEM5, are limited in assessing hardware-based tiered memory management solutions and handling real-world workloads at scale. 2) Previous memory tiering systems struggle to simultaneously achieve high resolution, low overhead, and high flexibility and compatibility. In this study, we first introduce HeteroBox, a configurable…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Cloud Computing and Resource Management · Advanced Data Storage Technologies
