3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
Cristian Sestito, Ahmed J. Abdelmaksoud, Shady Agwa, and Themis, Prodromakis

TL;DR
3D-TrIM introduces a memory-efficient 3D systolic array architecture for CNN accelerators, reducing memory access overhead and improving energy and area efficiency compared to previous designs.
Contribution
It proposes 3D-TrIM, an enhanced systolic array architecture with shadow registers and shared buffers, significantly reducing memory overhead and increasing efficiency for convolution workloads.
Findings
Achieves 4.47 TOPS/mm$^2$ area efficiency.
Attains 4.54 TOPS/W energy efficiency.
Outperforms TrIM by up to 3.37× in memory operations per CNN topology.
Abstract
The Von Neumann bottleneck, which relates to the energy cost of moving data from memory to on-chip core and vice versa, is a serious challenge in state-of-the-art AI architectures, like Convolutional Neural Networks' (CNNs) accelerators. Systolic arrays exploit distributed processing elements that exchange data with each other, thus mitigating the memory cost. However, when involved in convolutions, data redundancy must be carefully managed to avoid significant memory access overhead. To overcome this problem, TrIM has been recently proposed. It features a systolic array based on an innovative dataflow, where input feature map (ifmap) activations are locally reused through a triangular movement. However, ifmaps still suffer from memory accesses overhead. This work proposes 3D-TrIM, an upgraded version of TrIM that addresses the memory access overhead through few extra shadow registers.…
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Taxonomy
TopicsAdvanced Neural Network Applications · Parallel Computing and Optimization Techniques · Embedded Systems Design Techniques
