Kitsune: Enabling Dataflow Execution on GPUs

TL;DR

Kitsune introduces GPU architectural adjustments and a compiler to enable efficient dataflow execution, improving performance and reducing off-chip traffic for deep learning workloads without redesigning the hardware.

Contribution

The paper presents Kitsune, a novel set of primitives and a compiler that facilitate dataflow execution on GPUs, addressing limitations of traditional bulk-synchronous models.

Findings

Achieves 1.3×-2.3× performance improvement on challenge applications.

Reduces off-chip traffic by up to 98% during inference.

Provides 1.1×-2.4× performance gains during training.

Abstract

State of art DL models are growing in size and complexity, with many modern models also increasing in heterogeneity of behavior. GPUs are still the dominant platform for DL applications, relying on a bulk-synchronous execution model which has many drawbacks and is ill-suited for the graph structure of DL applications. Many industry and academic works attempt to overcome these by employing vertical fusion but this approach still fails to realize three untapped opportunities: (1) the fact that many resources on the GPU are idle while only one operator executes due to temporal multiplexing of the SM; (2) lower energy from more intelligent on-chip data-movement which lends to higher performance in a power-provisioned environment. (3) inability to exploit hidden or reduction dimensions as a source of parallelism to ease pressure on batch size. This paper explores relatively uncharted territory, answering the following key question: Can modest adjustments to the current GPU architecture enable efficient dataflow execution, thereby circumventing the constraints of vertical fusion without necessitating a clean-slate architecture design. We develop Kitsune -- a set of primitives that enable dataflow execution on GPUs and an end-to-end compiler based on PyTorch Dynamo. Across 5 challenge applications, Kitsune can provide 1.3$\times$-2.3$\times$ and 1.1$\times$-2.4$\times$ performance improvement as well as 41%-98% and 16%-42% off-chip traffic reduction for inference and training, respectively.