AxMED: Formal Analysis and Automated Design of Approximate Median Filters using BDDs

TL;DR

This paper presents a systematic design methodology for creating energy-efficient approximate median filters using BDDs, balancing accuracy, power, and area for FPGA implementations.

Contribution

It introduces a novel search-based approach and a new rank error metric for designing approximate median filters with optimized trade-offs.

Findings

Achieved 30% area reduction compared to exact median implementations.

Reduced power consumption by 36% with acceptable accuracy loss.

Demonstrated effectiveness on FPGA-based median filter designs.

Abstract

The increasing demand for energy-efficient solutions has led to the emergence of an approximate computing paradigm that enables power-efficient implementations in various application areas such as image and data processing. The median filter, widely used in image processing and computer vision, is of immense importance in these domains. We propose a systematic design methodology for the design of power-efficient median networks suitable for on-chip or FPGA-based implementations. A search-based design method is used to obtain approximate medians that show the desired trade-offs between accuracy, power consumption and area on chip. A new metric tailored to this problem is proposed to quantify the accuracy of approximate medians. Instead of the simple error rate, our method analyses the rank error. A significant improvement in implementation cost is achieved. For example, compared to the well-optimized high-throughput implementation of the exact 9-input median, a 30\% reduction in area and a 36\% reduction in power consumption was achieved by introducing an error by one position (i.e., allowing the 4th or 6th lowest input to be returned instead of the median).