Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice Support
Hannah Yang, Sohyeon Kim, Saeyeon Kim, Jiyoung Lee, Huijin Roh,, Ji-Hoon Kim

TL;DR
This paper introduces an optimized memory architecture for VESA VDC-M decoders that significantly reduces buffer sizes and hardware complexity while supporting real-time 4K UHD video decoding.
Contribution
It presents a novel memory system design with optimized scheduling and segmentation, achieving substantial buffer size reductions and hardware efficiency improvements.
Findings
33.3% reduction in line buffer size
77.3% reduction in reconstruction buffer size
Supports 4K UHD real-time decoding at 96.45 fps
Abstract
Video compression plays a pivotal role in managing and transmitting large-scale display data, particularly given the growing demand for higher resolutions and improved video quality. This paper proposes an optimized memory system architecture for Video Electronics Standards Association (VESA) Display Compression-M (VDC-M) decoder, characterized by its substantial on-chip buffer requirements. We design and analyze three architectures categorized by optimization levels and management complexity. Our strategy focuses on enhancing line buffer access scheduling and minimizing reconstruction buffer, targeting prediction and multi-slice operation that are the major resource consumers in the decoder. By adjusting line delay and segmenting SRAM bank alongside reconstructed block forwarding, we achieve a 33.3% size reduction in the line buffer and 77.3% in the reconstruction buffer compared to…
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Taxonomy
TopicsAdvanced Data Storage Technologies · Parallel Computing and Optimization Techniques · Error Correcting Code Techniques
