Ultrathin Ga$_2$O$_3$ Tunneling Contact for 2D Transition-metal Dichalcogenides Transistor

TL;DR

This paper introduces ultrathin Ga$_2$O$_3$ as an innovative tunneling contact layer for 2D TMD transistors, significantly reducing contact resistance and enhancing device performance for scalable electronics.

Contribution

It demonstrates a novel Ga$_2$O$_3$ tunneling contact that achieves near-ideal ohmic behavior and high mobility in WS$_2$ transistors, advancing contact engineering in 2D electronics.

Findings

Reduced contact resistance to 2.38 kΩ·μm

Achieved electron mobility of 296 cm²/V·s

Maintained high performance in large-scale arrays

Abstract

The development of two-dimensional (2D) transition metal dichalcogenides (TMDs) based transistors has been constrained by high contact resistance and inadequate current delivery, primarily stemming from metal-induced gap states and Fermi level pinning. Research into addressing these challenges is essential for the advancing 2D transistors from laboratory experiments to industrial-grade production. In this work, we present amorphous Ga$_2$O$_3$ as a novel tunneling contact layer for multilayer WS2-based field-effect transistors (FETs) to enhance electrical performance. The addition of this innovative tunneling layer avoid Schottky barrier forming while finally change into a tunneling barrier with the barrier height to just 3.7 meV, near-ideal ohmic contacts. This approach effectively reduces contact resistance to only 2.38 k$\Omega\,\mu$m and specific contact resistivity as low as $3 \times 10^{-5}$ $\Omega$cm$^2$. A record-high electron mobility of 296 cm$^2$ V$^{-1}$ s$^{-1}$ and ON-OFF ratio over 106 are realized for WS$_2$ transistor at room temperature. Compared to other tunneling materials, ultrathin Ga$_2$O$_3$ layer offers scalability, cost-efficient production and broad substrate compatibility, making it well-suited for seamless integration with industrial wafer-scale electronics. A robust device performance remains highly consistent in a large-scale transistor array fabricated on $1.5\times 1.5$ cm$^2$ chips, with the average mobility closing to 200 cm$^2$ V$^{-1}$ s$^{-1}$. These findings establish a new benchmark for contact performance in 2D transistors and prove the potential of tunneling contact engineering in advancing high-performance, scalable 29 pelectronics with promising applications in quantum computing and communication.