Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table
Haoyuan Wu, Haisheng Zheng, Shoubo Hu, Zhuolun He, Bei Yu

TL;DR
This paper introduces a novel method combining generative models and differentiable architecture search to improve circuit generation from truth tables, achieving better scalability and performance in logic synthesis.
Contribution
It presents CircuitVQ and CircuitAR, novel models that enhance circuit generation from truth tables, addressing limitations of existing methods with improved scalability and accuracy.
Findings
CircuitAR can generate complex circuit structures.
The method outperforms traditional logic synthesis tools.
Scalability and emergent capabilities demonstrated in experiments.
Abstract
Logic synthesis, a critical stage in electronic design automation (EDA), optimizes gate-level circuits to minimize power consumption and area occupancy in integrated circuits (ICs). Traditional logic synthesis tools rely on human-designed heuristics, often yielding suboptimal results. Although differentiable architecture search (DAS) has shown promise in generating circuits from truth tables, it faces challenges such as high computational complexity, convergence to local optima, and extensive hyperparameter tuning. Consequently, we propose a novel approach integrating conditional generative models with DAS for circuit generation. Our approach first introduces CircuitVQ, a circuit tokenizer trained based on our Circuit AutoEncoder We then develop CircuitAR, a masked autoregressive model leveraging CircuitVQ as the tokenizer. CircuitAR can generate preliminary circuit structures from…
Peer Reviews
Decision·Submitted to ICLR 2026
* Novel modeling approach of circuit generation from truth table using a masked autoregressive graph model.
* The primary utility of this work is reducing DAS search steps. This is a weaker utility compared to improving the quality of circuit optimization (fewer nodes or lower area/delay/power). * Quality comparison versus classical logic optimization algorithms such as resyn2 is not presented. Prior work such as ShortCircuit presents such comparisons.
- The "truth table - discrete tokens - adjacency matrix" pipeline is novel and technically solid. - The result shows that the performance of CircuitAR can scale with more parameters and tokens, which looks promising.
- The circuit size scalability of the proposed approach is questionable. No experimental result is shown about the circuit size scalability. The paper mentioned "a tenfold increase in circuit complexity compared to prior works", but it is not clear how this conclusion is drawn, and how the "circuit complexity" is measured (number of gates/PIs/POs?). It looks like all the circuits selected in table 1 and 2 are pretty small. - The number of sample circuits for evaluation is very small. In table 1
• A clear and interesting integration of masked autoregressive generation with DAS. The idea of using a generative prior to prune/guide the continuous search is sensible and novel in this space. • The training/evaluation pipeline is well illustrated, and the DAG projection routine is explicitly provided. • Empirical signal: Across ten IWLS’22 circuits, the approach reports substantial reductions in DAS steps and non trivial #NAND savings while keeping functional correctness. Scaling experime
• The main claims rely on 10 IWLS’22 circuits (Table 1–2, p.8). This is a small sample of the broader IWLS/EPFL/ISCAS landscape. • There is no comparison to industrial strength flows (e.g., ABC/Yosys scripts such as resyn2) in terms of final area/depth/delay under a standard cell library—even as a reference. The paper frames #NAND and “search space” but not mapped area/timing—which is what designers ultimately care about. • BitsD is measured as MAE of an untrained CircuitNN initialized by C
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Taxonomy
TopicsEvolutionary Algorithms and Applications
