Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment

TL;DR

This paper introduces MGVGA, a novel masked modeling approach for circuit representation learning that preserves logical equivalence and captures circuit functions using gate masking and Verilog-AIG alignment, improving logic synthesis tasks.

Contribution

The paper proposes MGVGA, combining masked gate modeling and Verilog-AIG alignment, to enhance circuit representation learning while maintaining logical equivalence and functional understanding.

Findings

MGVGA outperforms previous methods on logic synthesis tasks.

Masked gate modeling preserves logical equivalence.

Verilog-AIG alignment enables functional learning from LLMs.

Abstract

Understanding the structure and function of circuits is crucial for electronic design automation (EDA). Circuits can be formulated as And-Inverter graphs (AIGs), enabling efficient implementation of representation learning through graph neural networks (GNNs). Masked modeling paradigms have been proven effective in graph representation learning. However, masking augmentation to original circuits will destroy their logical equivalence, which is unsuitable for circuit representation learning. Moreover, existing masked modeling paradigms often prioritize structural information at the expense of abstract information such as circuit function. To address these limitations, we introduce MGVGA, a novel constrained masked modeling paradigm incorporating masked gate modeling (MGM) and Verilog-AIG alignment (VGA). Specifically, MGM preserves logical equivalence by masking gates in the latent space rather than in the original circuits, subsequently reconstructing the attributes of these masked gates. Meanwhile, large language models (LLMs) have demonstrated an excellent understanding of the Verilog code functionality. Building upon this capability, VGA performs masking operations on original circuits and reconstructs masked gates under the constraints of equivalent Verilog codes, enabling GNNs to learn circuit functions from LLMs. We evaluate MGVGA on various logic synthesis tasks for EDA and show the superior performance of MGVGA compared to previous state-of-the-art methods. Our code is available at https://github.com/wuhy68/MGVGA.