Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
O\u{g}uzhan Canpolat, A. Giray Ya\u{g}l{\i}k\c{c}{\i}, Geraldo F. Oliveira, Ataberk Olgun, Nisa Bostanc{\i}, \.Ismail Emir Y\"uksel, Haocong Luo, O\u{g}uz Ergin, Onur Mutlu

TL;DR
This paper introduces Chronus, a novel DRAM read disturbance mitigation mechanism that significantly improves performance and security over existing methods like PRAC by addressing their key weaknesses.
Contribution
Chronus is a new on-DRAM-die mitigation mechanism that updates counters concurrently and dynamically controls refreshes to prevent wave attacks, outperforming PRAC and other solutions.
Findings
Chronus achieves near-zero overhead on modern DRAMs.
Chronus outperforms PRAC and other state-of-the-art solutions.
PRAC has significant performance overhead and vulnerability to wave attacks.
Abstract
We 1) present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC) and 2) propose Chronus, a new mechanism that addresses PRAC's two major weaknesses. Our analysis shows that PRAC's system performance overhead on benign applications is non-negligible for modern DRAM chips and prohibitively large for future DRAM chips that are more vulnerable to read disturbance. We identify two weaknesses of PRAC that cause these overheads. First, PRAC increases critical DRAM access latency parameters due to the additional time required to increment activation counters. Second, PRAC performs a constant number of preventive refreshes at a time, making it vulnerable to an adversarial access pattern, known as the wave attack, and consequently requiring it to be configured for…
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Taxonomy
Topics3D IC and TSV technologies · Advanced Data Storage Technologies
