Nexus Machine: An Active Message Inspired Reconfigurable Architecture for Irregular Workloads

TL;DR

Nexus Machine introduces a reconfigurable architecture that dynamically manages irregular workloads like sparse linear algebra and graph analytics, significantly improving performance and fabric utilization over existing architectures.

Contribution

It presents a novel PE array design with active message-based instruction morphing and dynamic load balancing to better handle irregular workloads.

Findings

Achieves 90% better performance than SOTA architectures.

Attains 70% higher fabric utilization.

Effectively mitigates load imbalance in irregular workloads.

Abstract

Modern reconfigurable architectures are increasingly favored for resource-constrained edge devices as they balance high performance, energy efficiency, and programmability well. However, their proficiency in handling regular compute patterns constrains their effectiveness in executing irregular workloads, such as sparse linear algebra and graph analytics with unpredictable access patterns and control flow. To address this limitation, we introduce the Nexus Machine, a novel reconfigurable architecture consisting of a PE array designed to efficiently handle irregularity by distributing sparse tensors across the fabric and employing active messages that morph instructions based on dynamic control flow. As the inherent irregularity in workloads can lead to high load imbalance among different Processing Elements (PEs), Nexus Machine deploys and executes instructions en-route on idle PEs at run-time. Thus, unlike traditional reconfigurable architectures with only static instructions within each PE, Nexus Machine brings dynamic control to the idle compute units, mitigating load imbalance and enhancing overall performance. Our experiments demonstrate that Nexus Machine achieves 90% better performance compared to state-of-the-art (SOTA) reconfigurable architectures, within the same power budget and area. Nexus Machine also achieves 70% higher fabric utilization, in contrast to SOTA architectures.