Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Yahya Can Tu\u{g}rul, A. Giray Ya\u{g}l{\i}k\c{c}{\i}, \.Ismail Emir, Y\"uksel, Ataberk Olgun, O\u{g}uzhan Canpolat, Nisa Bostanc{\i}, Mohammad, Sadrosadati, O\u{g}uz Ergin, Onur Mutlu

TL;DR
This paper experimentally investigates the effects of reduced refresh latency on RowHammer in real DRAM chips, proposing a low-cost mitigation mechanism that improves performance and energy efficiency.
Contribution
It provides the first experimental analysis of refresh latency impact on RowHammer and introduces PaCRAM, a novel mitigation mechanism leveraging these insights.
Findings
Reduced refresh latency by 64% in real DRAM chips.
PaCRAM effectively lowers performance and energy overheads.
Open-source implementation available for future research.
Abstract
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). To ensure robust DRAM operation, state-of-the-art mitigation mechanisms restore the charge in potential victim rows (i.e., they perform preventive refresh or charge restoration). With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads. Therefore, it is essential to develop a better understanding and in-depth insights into the preventive refresh to secure real DRAM chips at low cost. In this paper, our goal is to mitigate RowHammer at low cost by understanding the impact of reduced preventive refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions…
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Taxonomy
TopicsAdvanced Data Storage Technologies · Green IT and Sustainability · 3D IC and TSV technologies
