Non-Binary LDPC Arithmetic Error Correction For Processing-in-Memory
Daijing Shi, Yihang Zhu, Anjunyi Fan, Yaoyu Tao, Yuchao Yang, Bonan, Yan

TL;DR
This paper introduces a non-binary LDPC error correction scheme for processing-in-memory systems, significantly improving reliability and power efficiency in memristor-based PIM by correcting multiple errors with high code rate.
Contribution
It proposes a novel NB-LDPC error correction method compatible with PIM, demonstrating high error correction capability and power efficiency improvements through a fabricated prototype.
Findings
Up to 8-bit error correction with 88% code rate
59.65x BER improvement over uncorrected PIM
2.978x power efficiency enhancement
Abstract
Processing-in-memory (PIM) based on emerging devices such as memristors is more vulnerable to noise than traditional memories, due to the physical non-idealities and complex operations in analog domains. To ensure high reliability, efficient error-correcting code (ECC) is highly desired. However, state-of-the-art ECC schemes for PIM suffer drawbacks including dataflow interruptions, low code rates, and limited error correction patterns. In this work, we propose non-binary low-density parity-check (NB-LDPC) error correction running over the Galois field. Such NB-LDPC scheme with a long word length of 1024 bits can correct up to 8-bit errors with a code rate over 88%. Nonbinary GF operations can support both memory mode and PIM mode even with multi-level memory cells. We fabricate a 40nm prototype PIM chip equipped with our proposed NB-LDPC scheme for validation purposes. Experiments show…
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Taxonomy
TopicsError Correcting Code Techniques · Neural Networks and Reservoir Computing · Quantum Computing Algorithms and Architecture
