A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks

TL;DR

This paper presents a hybrid analog-digital compute-in-memory architecture that significantly improves energy efficiency and accuracy for high-precision deep neural network acceleration, addressing power consumption issues of digital-only CIM solutions.

Contribution

It introduces a novel hybrid domain CIM architecture combining analog and digital methods within the same memory cell for high-precision DNNs.

Findings

Demonstrates high energy efficiency through circuit-level simulations

Achieves lossless accuracy on benchmark tests

Develops area-efficient and energy-efficient ADC techniques

Abstract

Compute-in-memory (CIM) has shown significant potential in efficiently accelerating deep neural networks (DNNs) at the edge, particularly in speeding up quantized models for inference applications. Recently, there has been growing interest in developing floating-point-based CIM macros to improve the accuracy of high-precision DNN models, including both inference and training tasks. Yet, current implementations rely primarily on digital methods, leading to substantial power consumption. This paper introduces a hybrid domain CIM architecture that integrates analog and digital CIM within the same memory cell to efficiently accelerate high-precision DNNs. Specifically, we develop area-efficient circuits and energy-efficient analog-to-digital conversion techniques to realize this architecture. Comprehensive circuit-level simulations reveal the notable energy efficiency and lossless accuracy of the proposed design on benchmarks.