A nested MLMC framework for efficient simulations on FPGAs

TL;DR

This paper introduces a novel FPGA-based MLMC framework that leverages low precision calculations and approximate random variables to significantly reduce computational costs and power consumption in financial simulations.

Contribution

The paper presents a new MLMC framework optimized for FPGAs that uses approximate random variables and fixed-point operations to enhance efficiency over existing methods.

Findings

Higher computational savings than existing mixed-precision MLMC frameworks

Effective use of approximate random variables for cost reduction

Optimized variable precision based on a rounding error model

Abstract

Multilevel Monte Carlo (MLMC) reduces the total computational cost of financial option pricing by combining SDE approximations with multiple resolutions. This paper explores a further avenue for reducing cost and improving power efficiency through the use of low precision calculations on configurable hardware devices such as Field-Programmable Gate Arrays (FPGAs). We propose a new framework that exploits approximate random variables and fixed-point operations with optimised precision to generate most SDE paths with a lower cost and reduce the overall cost of the MLMC framework. We first discuss several methods for the cheap generation of approximate random Normal increments. To set the bit-width of variables in the path generation we then propose a rounding error model and optimise the precision of all variables on each MLMC level. With these key improvements, our proposed framework offers higher computational savings than the existing mixed-precision MLMC frameworks.