Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture

TL;DR

This paper introduces new quantum circuit mapping strategies for silicon spin qubits in a shuttling bus architecture, aiming to minimize errors and execution time in scalable quantum computing.

Contribution

It proposes and evaluates five mapping algorithms, highlighting the Swap Return strategy as the most effective for balancing error reduction and speed.

Findings

Swap Return strategy outperforms others in robustness

Informed initial qubit placement improves dynamic mapping performance

Optimized shuttling reduces phase errors and circuit execution time

Abstract

In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.