Characterization and Mitigation of ADC Noise by Reference Tuning in RRAM-Based Compute-In-Memory
Ying-Hao Wei, Zishen Wan, Brian Crafton, Samuel Spetalnick, Arijit, Raychowdhury

TL;DR
This paper presents a comprehensive noise model for RRAM-based compute-in-memory systems, demonstrating how reference tuning can effectively mitigate ADC and device noise impacts on neural network accuracy.
Contribution
It introduces a detailed noise model incorporating ADC and RRAM device variability, and proposes reference tuning as a mitigation strategy for noise in CIM architectures.
Findings
Reference tuning reduces noise-induced errors in neural network inference.
Low-voltage read mode mitigates read-disturb effects on RRAM devices.
The model accurately predicts noise impact on both supervised and reinforcement learning tasks.
Abstract
With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a critical concern. This study confronts this challenge by introducing a detailed model that incorporates noise factors arising from both ADCs and RRAM devices. The experimental data is derived from a 40nm foundry RRAM test-chip, wherein different reference voltage configurations are applied, each tailored to its respective module. The mean and standard deviation values of HRS and LRS cells are derived through a randomized vector, forming the foundation for noise simulation within our analytical framework. Additionally, the study examines the read-disturb effects, shedding light on the potential for accuracy deterioration in neural networks due to…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices
