An Arbitrary Time Interval Generator Base on Vernier Clocks with 0.67 ps Adjustable Steps Implemented in FPGA

TL;DR

This paper presents a digital scheme using vernier clocks generated by cascaded PLLs in FPGA to produce highly precise, adjustable time intervals with steps as small as 0.67 ps, overcoming limitations of delay cell-based methods.

Contribution

A novel FPGA-based digital approach utilizing vernier clocks for ultra-fine adjustable time intervals with sub-picosecond resolution.

Findings

Achieved 0.67 ps adjustable steps in FPGA implementation.

Demonstrated scheme's robustness across different FPGA families.

Validated precise timing control in TDC testing applications.

Abstract

In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the cells, which are typically 15 to 20 picoseconds per step and are sensitive to temperature and operating voltage. In this document, a purely digital scheme based on two vernier clocks with small frequency difference generated using cascaded PLL is reported. The scheme is tested in two families of low-cost FPGA and 0.67 and 0.97 picoseconds adjustable steps of the time intervals are achieved.