Performance studies of the CE-65v2 MAPS prototype structure
A. Ilg (1), A. Lorenzetti (1), H. Baba (2), J. Baudot (3), A. Besson, (3), S. Bugiel (3), T. Chujo (4), C. Colledani (3), A. Dorokhov (3), Z. El, Bitar (3), M. Goffe (3), T. Gunji (2), C. Hu-Guo (3), K. Jaaskelainen (3), T., Katsuno (5), A. Kluge (6), A. Kostina (7)

TL;DR
This study evaluates the charge collection, efficiency, and spatial resolution of the CE-65v2 MAPS prototype, demonstrating high efficiency and sub-3 micron resolution suitable for future vertex detectors, through extensive beam testing and in-pixel analysis.
Contribution
It provides a detailed characterization of the CE-65v2 MAPS prototype, including in-pixel performance and effects of process variants, advancing the development of high-resolution vertex detectors.
Findings
Hit efficiencies of ≥99% achieved across variants
Spatial resolution below 3 μm for standard process
Large sensor size enables detailed in-pixel performance analysis
Abstract
With the next upgrade of the ALICE inner tracking system (ITS3) as its primary focus, a set of small MAPS test structures have been developed in the 65 nm TPSCo CMOS process. The CE-65 focuses on the characterisation of the analogue charge collection properties of this technology. The latest iteration, the CE-65v2, was produced in different processes (standard, with a low-dose n-type blanket, and blanket with gap between pixels), pixel pitches (15, 18, 22.5 m), and pixel arrangements (square or staggered). The comparatively large pixel array size of pixels in CE-65v2 allows the uniformity of the pixel response to be studied, among other benefits. The CE-65v2 chip was characterised in a test beam at the CERN SPS. A first analysis showed that hit efficiencies of and spatial resolution better than 5 m can be achieved for all pitches and process…
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Taxonomy
TopicsSilicon and Solar Cell Technologies
