Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables
Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh, Harjani, Sachin S. Sapatnekar

TL;DR
This paper introduces a transformer-based framework for automated transistor sizing in OTAs, significantly reducing simulation time and improving efficiency by predicting parameters with minimal SPICE simulations.
Contribution
It presents a novel transformer model combined with lookup tables for fast, accurate OTA transistor sizing, outperforming traditional and machine learning methods.
Findings
Achieves over 90% success with one SPICE simulation
Attains 100% success with 3-5 additional simulations
Reduces reliance on expensive SPICE simulations during optimization
Abstract
Device sizing is crucial for meeting performance specifications in operational transconductance amplifiers (OTAs), and this work proposes an automated sizing framework based on a transformer model. The approach first leverages the driving-point signal flow graph (DP-SFG) to map an OTA circuit and its specifications into transformer-friendly sequential data. A specialized tokenization approach is applied to the sequential data to expedite the training of the transformer on a diverse range of OTA topologies, under multiple specifications. Under specific performance constraints, the trained transformer model is used to accurately predict DP-SFG parameters in the inference phase. The predicted DP-SFG parameters are then translated to transistor sizes using a precomputed look-up table-based approach inspired by the gm/Id methodology. In contrast to previous conventional or…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · VLSI and FPGA Design Techniques · Low-power high-performance VLSI design
