Exploration of optimized front-end readout circuit for time measurement of large-area SiPM arrays

TL;DR

This paper develops and tests optimized front-end readout circuits for large-area SiPM arrays, achieving high timing resolution and low power consumption suitable for deep-sea neutrino detection.

Contribution

It introduces four novel ASIC architectures with different input stages and discriminators, optimized for high-resolution time measurement of large-area SiPM arrays.

Findings

Achieved ~260 ps FWHM single photon time resolution.

Timing jitter less than 500 ps FWHM for 6x6 mm^2 SiPM array.

Power consumption under 7 mW per channel.

Abstract

The detector of TRopIcal DEep-sea Neutrino Telescope (TRIDENT) will use large-area silicon photomultiplier (SiPM) arrays combined with photomultiplier tubes to boost photon detection efficiency and pointing capability. An application-specific integrated circuit (ASIC) is being developed to aim at high-resolution time measurement of large-area SiPM arrays. This work researches four architectures of readout circuits including different input stages (common gate stage and negative feedback common gate stage) and discriminators (two types of current discriminator and one voltage discriminator) using a 180 nm CMOS process for optimizing time resolution. The experimental measurements show that single photon time resolutions performed using Hamamatsu S13360-3050PE SiPMs are around 260 ps full width at half maximum (FWHM). A timing jitter less than 500 ps FWHM when connecting a 6x6 mm^2 SiPM array is achieved. The power consumption is less than 7 mW/channel. Additionally, a digital summation is applied to reduce the number of output interfaces. The measured performances of the ASIC cater to the TRIDENT application requirements.