Random Telegraph Noise of MIS and MIOS Silicon Nitride memristors at different resistance states

TL;DR

This study investigates the random telegraph noise in silicon nitride memristors at multiple resistance states, revealing insights into their stochastic behavior and potential security applications.

Contribution

It introduces a CMOS-compatible memristor model with multi-level resistance states and analyzes noise characteristics to understand defect-related switching mechanisms.

Findings

Four stable resistance states identified

Noise signals linked to silicon nitride defects

Model explaining defect influence on noise

Abstract

Resistive memories (RRAM) are promising candidates for replacing present nonvolatile memories and realizing storage class memories; hence resistance switching devices are of particular interest. These devices are typically memristive, with a large number of discrete resistance levels and in some configurations, they perform as analog memories. Noise studies have been used to enlighten further the resistance switching mechanism in these devices. Recently, a strong interest arose on the noise generated by RRAM/memristors because due to their inherent stochasticity can be used for cryptography and other security applications. In this work, two fully CMOS compatible memristive devices both with silicon nitride as switching material, were examined in terms of multi-level resistance operation. Using appropriate SET/RESET pulse sequences through a flexible analog tuning protocol, four stable resistance states were investigated through random telegraph noise measurements and analysis. A possible model enlightening the role of silicon nitride defects in the observed noise signals at different resistive states is presented.