DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale
Ziyang Zheng, Shan Huang, Jianyuan Zhong, Zhengyuan Shi, Guohao Dai, Ningyi Xu, Qiang Xu
TL;DR
DeepGate4 is a novel graph transformer model designed for large-scale circuit representation learning, offering significant improvements in scalability, efficiency, and performance over existing methods in electronic design automation tasks.
Contribution
We introduce DeepGate4, a scalable graph transformer with innovative update strategies and sparse attention mechanisms tailored for large circuit graphs, reducing complexity and enhancing performance.
Findings
Achieves 15.5% and 31.1% performance improvements on benchmarks.
Reduces runtime by 35.1% and memory usage by 46.8%.
Demonstrates superior scalability and efficiency for large-scale circuit analysis.
Abstract
Circuit representation learning has become pivotal in electronic design automation, enabling critical tasks such as testability analysis, logic reasoning, power estimation, and SAT solving. However, existing models face significant challenges in scaling to large circuits due to limitations like over-squashing in graph neural networks and the quadratic complexity of transformer-based models. To address these issues, we introduce DeepGate4, a scalable and efficient graph transformer specifically designed for large-scale circuits. DeepGate4 incorporates several key innovations: (1) an update strategy tailored for circuit graphs, which reduce memory complexity to sub-linear and is adaptable to any graph transformer; (2) a GAT-based sparse transformer with global and local structural encodings for AIGs; and (3) an inference acceleration CUDA kernel that fully exploit the unique sparsity…
Peer Reviews
Decision·ICLR 2025 Poster
1. The experimental evaluation is comprehensive and compelling, showing significant performance improvements over state-of-the-art baselines. The empirical results strongly validate the effectiveness of the proposed approach, with substantial gains across multiple metrics and circuit scales. 2. The technical contribution is substantial. The work demonstrates innovation in addressing fundamental scalability challenges in circuit analysis through: a. A novel graph partitioning strategy b. An e
1. The results of the experiment can be represented more visually in graphs. It will be better if the authors could explain in detail the parameter settings in the ablation experiment. For example, why was the parameter k set to 8? 2. It is mentioned that the loss balancer is very effective in reducing the loss, can the authors expand more on this or give a theoretical analysis? And it will be better if the authors could analyze why the loss balancer must be introduced in the last layer. 3、The d
This paper addresses a fundamental problem in machine learning for electronic design automation. The proposed DeepGate4 consists of several interesting and effective modules to improve the scalability of the method. Experimental results demonstrate a significant improvement.
The novelty of the proposed graph partitioning method and the loss balancer is limited. The graph partition mechanism is a commonly-used technique for handling large-scale industrial circuits. Moreover, the dynamic loss balancer has been widely investigated in computer vision [1]. The OpenABC-D benchmark is widely-used in previous work. Can the authors evaluate their method on this benchmark as well. A recent SOTA method called HOGA [2] also addresses the challenge of scaling to large-scale ci
1. Circuit representation learning is an interesting and important research topic. 2. Experiments demonstrate the proposed method significantly outperforms baselines.
1. The writing could be improved. (1) It would be more readable if the authors could provide a summary of contributions. (2) The method description is unclear. For example, the graph partition module and the multi-task training objective is unclear. 2. The novelty of the proposed method is unclear. The authors incorporates many modules into previous circuit representation learning method. However, the novelty and contribution of these modules seems limited. 3. Experiments are insufficient. (1
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Taxonomy
TopicsVLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing · 3D IC and TSV technologies
MethodsAttention Is All You Need · Cosine Annealing · Label Smoothing · Byte Pair Encoding · Position-Wise Feed-Forward Layer · Adam · Softmax · Laplacian EigenMap · Dropout · Absolute Position Encodings