Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression

TL;DR

This paper presents a structured compression approach for photonic neural networks, significantly reducing hardware complexity and power consumption while maintaining accuracy, thus enabling scalable and efficient optical AI accelerators.

Contribution

Introduction of a block-circulant photonic tensor core with a hardware-aware training framework for structure-compressed optical neural networks.

Findings

Up to 74.91% reduction in trainable parameters.

Achieved 3.56 times improvement in power efficiency.

Maintained competitive accuracy with compressed models.

Abstract

The rapid growth in computing demands, particularly driven by artificial intelligence applications, has begun to exceed the capabilities of traditional electronic hardware. Optical computing offers a promising alternative due to its parallelism, high computational speed, and low power consumption. However, existing photonic integrated circuits are constrained by large footprints, costly electro-optical interfaces, and complex control mechanisms, limiting the practical scalability of optical neural networks (ONNs). To address these limitations, we introduce a block-circulant photonic tensor core for a structure-compressed optical neural network (StrC-ONN) architecture. The structured compression technique substantially reduces both model complexity and hardware resources without sacrificing the versatility of neural networks, and achieves accuracy comparable to uncompressed models. Additionally, we propose a hardware-aware training framework to compensate for on-chip nonidealities to improve model robustness and accuracy. Experimental validation through image processing and classification tasks demonstrates that our StrC-ONN achieves a reduction in trainable parameters of up to 74.91%,while still maintaining competitive accuracy levels. Performance analyses further indicate that this hardware-software co-design approach is expected to yield a 3.56 times improvement in power efficiency. By reducing both hardware requirements and control complexity across multiple dimensions, this work explores a new pathway toward practical and scalable ONNs, highlighting a promising route to address future computational efficiency challenges.