Function Approximation Using Analog Building Blocks in Flexible Electronics

TL;DR

This paper presents an analog hardware approach for function approximation in flexible electronics, using basic building blocks to create efficient, low-area, and low-power computational units suitable for constrained devices.

Contribution

It introduces a systematic method combining analog building blocks to implement Kolmogorov-Arnold Networks, offering a hardware-efficient alternative to digital solutions in flexible electronics.

Findings

125x reduction in area compared to digital spline implementations

10.59% power savings over digital counterparts

Approximation error up to 7.58% due to design and parasitics

Abstract

Function approximation is crucial in Flexible Electronics (FE), where applications demand efficient computational techniques within strict constraints on size, power, and performance. Devices like wearables and compact sensors are constrained by their limited physical dimensions and energy capacity, making traditional digital function approximation challenging and hardware-demanding. This paper addresses function approximation in FE by proposing a systematic and generic approach using a combination of Analog Building Blocks (ABBs) that perform basic mathematical operations such as addition, multiplication, and squaring. These ABBs serve as the foundation for constructing splines, which are then employed in the creation of Kolmogorov-Arnold Networks (KANs), improving the approximation. The analog realization of KAN offers a promising alternative to digital solutions, providing significant hardware benefits, particularly in terms of area and power consumption. Our design achieves a 125x reduction in area and a 10.59% power saving compared to a digital spline with 8-bit precision. Results also show that the analog design introduces an approximation error of up to 7.58% due to both the design and parasitic elements. Nevertheless, KANs are shown to be a viable candidate for function approximation in FE, with potential for further optimization to address the challenges of error reduction and hardware cost.