PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies

TL;DR

PlaceIT is a new method that jointly optimizes chiplet placement and inter-chiplet interconnect topology to reduce latency and improve throughput in 2.5D stacked chips, outperforming traditional fixed-topology approaches.

Contribution

It introduces a novel approach that generates placement-based interconnect topologies tailored to specific chiplet placements, unlike prior methods that optimize placement for fixed topologies.

Findings

Reduces synthetic traffic latency by up to 28% (L1-L2) and 62% (L2-memory).

Achieves up to 18% packet latency reduction on traffic traces.

Supports optimization for homogeneous and heterogeneous chiplet shapes.

Abstract

2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-chiplet interconnect (ICI). Two major factors affecting the latency and throughput are the topology of links between chiplets and the chiplet placement. In this work, we present PlaceIT, a novel methodology to jointly optimize the ICI topology and the chiplet placement. While state-of-the-art methods optimize the chiplet placement for a predetermined ICI topology, or they select one topology out of a set of candidates, we generate a completely new topology for each placement. Our process of inferring placement-based ICI topologies connects chiplets that are in close proximity to each other, making it particularly attractive for chips with silicon bridges or passive silicon interposers with severely limited link lengths. We provide an open-source implementation of our method that optimizes the placement of homogeneously or heterogeneously shaped chiplets and the ICI topology connecting them for a user-defined mix of four different traffic types. We evaluate our methodology using synthetic traffic and traces, and we compare our results to a 2D mesh baseline. PlaceIT reduces the latency of synthetic L1-to-L2 and L2-to-memory traffic, the two most important types for cache coherency traffic, by up to 28% and 62%, respectively. It also achieve an average packet latency reduction of up to 18% on traffic traces. PlaceIT enables the construction of 2.5D stacked chips with low-latency ICIs.