Theoretical complexity analysis of many-cores on a single chip

TL;DR

This paper provides a theoretical analysis of many-core architectures on a single chip, showing how speedup, power, and energy scale with the number of cores, highlighting their efficiency advantages.

Contribution

It introduces a theoretical framework quantifying the performance and energy efficiency benefits of scaling to many-core architectures on a single chip.

Findings

Speedup scales as √m with m cores.

Power consumption decreases as √m.

Energy consumption reduces linearly with m.

Abstract

When a single core is scaled up to m cores occupying the same chip area and executing the same (parallelizable) task, achievable speedup is square-root m, power is reduced by square-root m and energy is reduced by m. Thus, many-core architectures can efficiently outperform architectures of a single core and a small-count multi-core.