Efficient Read-Port-Count Reduction Schemes for the Centralized Physical Register File in a Superscalar Microprocessor

TL;DR

This paper proposes a practical method for designing low-complexity read-port reduction schemes for centralized physical register files in superscalar CPUs, significantly reducing port count with minimal performance loss.

Contribution

It introduces a high-level analysis approach and a practical construction method for low-complexity port reduction schemes in register files.

Findings

Read-port count reduced from 17 to 8 with minimal performance impact.

Performance degradation of only 0.1% IPC on SPECrate CPU 2017 workloads.

Method achieves a twofold reduction in read ports while maintaining efficiency.

Abstract

The physical register file supports increasing the execution width and depth of a superscalar microprocessor to exploit more instruction-level parallelism. The efficient design of the physical register file is critical since its resources, such as the number of read and write ports, have a significant impact on CPU power consumption. Reducing the number of ports to the physical register file is a well-known direction for optimization. For port-count reduction schemes, balancing the trade-off between the scheme's complexity and performance is crucial. In our work, we introduce a high-level analysis method to estimate the complexity of the schemes during microarchitectural design. Moreover, we explore the structure of different port-count reduction schemes and introduce a practical approach to constructing low-complexity read-portcount reduction schemes for the centralized integer physical register file. We show that the read-port-count reduction schemes designed with this approach can reduce the number of read ports by a factor of two (from 17 to 8 read ports) with the Geomean performance degradation of only 0.1% IPC across the SPECrate CPU 2017 Integer workloads.