Analysis of a Memcapacitor-Based for Neural Network Accelerator Framework

TL;DR

This paper presents a novel memcapacitor-based hardware framework for neural network acceleration, demonstrating high accuracy in digit and image classification tasks, and explores its potential for energy-efficient neuromorphic computing.

Contribution

Introduces a CMOS-based memcapacitor circuit and a memcapacitive accelerator framework validated through simulations and testing, advancing hardware for neural network processing.

Findings

Achieved 98.4% accuracy in digit classification

Achieved 94.4% accuracy in CIFAR dataset recognition

Validated the memcapacitor device and system performance

Abstract

Data-intensive computing tasks, such as training neural networks, are crucial for artificial intelligence applications but often come with high energy demands. One promising solution is to develop specialized hardware that directly maps neural networks, utilizing arrays of memristive devices to perform parallel multiply-accumulate operations. In our research, we introduce a novel CMOS-based memcapacitor circuit that is validated using the cadence tool. Additionally, we developed the device in Python to facilitate the design of a memcapacitive-based accelerator. Our proposed framework employs a crossbar array of memcapacitor devices to train a neural network capable of digit classification and CIFAR dataset recognition. We tested the non-ideal characteristics of the constructed memcapacitor-based neural network. The system achieved an impressive 98.4% training accuracy in digit recognition and 94.4% training accuracy in CIFAR recognition, highlighting its effectiveness. This study demonstrates the potential of memcapacitor-based neural network systems in handling classification tasks and sets the stage for further advancements in neuromorphic computing.